Silicon Wafer EngineeringFuture of AI & Visionary Thinking
Time crystals and visionary AI in silicon wafer engineering: separating physics from speculation
A time crystal is a quantum system, driven by a periodic force, that settles into a rhythm of its own — repeating at a longer period than the drive and holding that rhythm against perturbation. For silicon wafer engineering the honest question is narrower: which manufacturing disciplines that physics demands are already worth building today?

Key takeaways
- A discrete time crystal is a real, reproduced phenomenon — but only in periodically driven systems. Equilibrium time crystals were ruled out by a published no-go theorem (Watanabe and Oshikawa, 2015), and no published result claims net energy extraction. Any roadmap that treats a time crystal as a power source or an off-the-shelf component is wrong at the physics, not merely optimistic.
- The one load-bearing connection between time-crystal physics and a wafer fab is quantum-device fabrication on silicon, and it is already industrial: Intel, imec and CEA-Leti have all published 300 mm spin-qubit fabrication using standard high-volume lithography, deposition and production-level process control.
- Every capability a coherence-grade line would demand — isotopic purity control, sub-2 nm CD uniformity, wafer-scale electrical screening, drift-aware run-to-run control — pays for itself on the logic and memory you ship today. Future-readiness here is overwhelmingly present-readiness.
- The fab discipline the metaphor actually names is phase stability: whether a periodic operating rhythm — PM, wet clean, seasoning, qualification, controller update — survives a perturbation without amplifying it. Most fabs can draw the rhythm. Very few measure how long it takes to re-lock after it breaks.
- Visionary claims are useful only when they are bounded. State the physics bound, the certification bound and the demand bound alongside every future claim, and the difference between a credible roadmap and a vendor deck becomes visible in a single reading.
Abbreviations used on this page
- APC
- Advanced process control
- R2R
- Run-to-run control (per-lot feedback on a recipe parameter)
- EWMA
- Exponentially weighted moving average — the standard R2R filter
- VM
- Virtual metrology — predicting a measurement instead of taking it
- FDC
- Fault detection and classification (tool sensor traces)
- SPC
- Statistical process control
- CD
- Critical dimension — the feature width a process must hold
- PM
- Preventive maintenance
- MES
- Manufacturing execution system
- EDA
- Equipment data acquisition — the SEMI Interface A / E120-series tool feed
- HVM
- High-volume manufacturing
- DTC
- Discrete time crystal — the driven, subharmonic kind that has been observed
Free · 8 questions · ~3 minutes
Score your line's phase stability
Eight questions, one at a time, about three minutes. They ask how well your fab sees, holds and recovers its own periodic rhythms — cycle instrumentation, phase control, perturbation recovery and coherence-grade discipline. Answer them and we build your personalised report: your rung on the ladder, your score on each dimension, and the specific thing standing between you and the next rung.
0 of 8 answered
Pick an option to continue
Report ready
Your personalised report is ready
Tell us where to send it. Your rung appears on screen immediately, and the full report — dimension scores, the modules where phase stability usually leaks first for a line like yours, and a 90-day plan for your weakest dimension — arrives by email.
Your result
Your full report is on its way to your inbox.
Stage 1 · Calendar cadence
Calendar cadence is a fab whose periodic work — PM, wet clean, seasoning, qualification, calibration — fires on a fixed interval, with no measured account of what the process does between firings.
Your next moveReconstruct the in-cycle trace for one chamber — metrology result against wafers-since-clean and hours-since-PM, six months deep — and agree what counts as a cycle reset.
Stage 2 · Measured drift
Measured drift is a fab that can see the shape of its own cycles — the sawtooth between cleans, the decay across pad life, the walk across source hours — but still corrects them by hand.
Your next movePut cycle position into one virtual-metrology model and one run-to-run controller as an explicit feature, rather than leaving it as a hidden confound.
Stage 3 · Phase-locked control
Phase-locked control is where periodic structure lives inside the control loop: prediction and run-to-run correction both know where in the cycle a wafer sits, and cadence is triggered by predicted state rather than by the calendar.
Your next moveStart measuring re-lock time: the wafers or hours between a perturbation and the process returning inside its normal band, per module and per perturbation type.
Stage 4 · Perturbation-resilient operations
Perturbation-resilient operations is where the fab measures how long its rhythm takes to return after a shock, manages that recovery time as a number, and knows whether a disturbance amplifies downstream or dies out.
Your next moveDecide deliberately whether any product line justifies coherence-grade tolerances — and if none does, keep rungs 1–4 paying rather than manufacturing a reason to go further.
Stage 5 · Coherence-grade manufacturing
Coherence-grade manufacturing is a line held tightly enough, and evidenced well enough, to make devices whose function depends on quantum coherence — the standard the published 300 mm silicon spin-qubit programmes are built to.
Your next moveBuy optionality through research partnership and shuttle runs rather than through dedicated capacity, and keep the rung-1-to-4 disciplines earning on current products.
0 / 24
Cadence instrumentation
— / 6
Phase control
— / 6
Perturbation recovery
— / 6
Coherence-grade discipline
— / 6
Your score maps to a rung on the phase-stability ladder. The dimension breakdown matters more than the total: the lowest dimension is what actually caps you, and on this ladder it is almost always cadence instrumentation rather than control sophistication. Your lowest-scoring dimension is —, and that is where the next investment belongs.
Your score maps to a rung on the phase-stability ladder. The dimension breakdown matters more than the total: the lowest dimension is what actually caps you, and on this ladder it is almost always cadence instrumentation rather than control sophistication.Your four dimensions score evenly, so there is no single weak link to attack — follow the stage’s next move above rather than picking a dimension.
Want this checked against your actual telemetry?
We take three modules, pull the cycle-state and metrology history you already record, and measure re-lock time, in-cycle drift and controller correction behaviour directly. It usually revises the internal view of where the line sits, in both directions, and you keep the measurements either way.
How the score maps to a stage
- 0–4 — Stage 1, Calendar cadence. Calendar cadence is a fab whose periodic work — PM, wet clean, seasoning, qualification, calibration — fires on a fixed interval, with no measured account of what the process does between firings.
- 5–9 — Stage 2, Measured drift. Measured drift is a fab that can see the shape of its own cycles — the sawtooth between cleans, the decay across pad life, the walk across source hours — but still corrects them by hand.
- 10–14 — Stage 3, Phase-locked control. Phase-locked control is where periodic structure lives inside the control loop: prediction and run-to-run correction both know where in the cycle a wafer sits, and cadence is triggered by predicted state rather than by the calendar.
- 15–19 — Stage 4, Perturbation-resilient operations. Perturbation-resilient operations is where the fab measures how long its rhythm takes to return after a shock, manages that recovery time as a number, and knows whether a disturbance amplifies downstream or dies out.
- 20–24 — Stage 5, Coherence-grade manufacturing. Coherence-grade manufacturing is a line held tightly enough, and evidenced well enough, to make devices whose function depends on quantum coherence — the standard the published 300 mm silicon spin-qubit programmes are built to.
What a time crystal is — and what it has to do with a wafer fab
A definition, the published evidence and its bounds, and a ledger that separates established physics from research claims from speculation.
A time crystal is a many-body quantum system that, when driven by a periodic force, settles into a periodic behaviour of its own at a different — usually longer — period than the drive, and holds that rhythm against small perturbations. The name is an analogy with an ordinary crystal: an ordinary crystal breaks the continuous symmetry of space by picking out a repeating spatial pattern, and a time crystal breaks a symmetry of time by picking out a repeating temporal one. The version that has actually been observed is the discrete time crystal (opens in a new tab), which exists only in driven, out-of-equilibrium systems.
Two bounds have to travel with that definition or it becomes nonsense. First, there is no equilibrium version: Watanabe and Oshikawa proved a no-go theorem (opens in a new tab) ruling out time-crystalline order in the ground state of a system in thermal equilibrium, which is why every observed example sits in a driven system. Second, a time crystal is not a source of energy. The drive supplies energy continuously; what is remarkable is the period and the robustness of the response, not the energy balance. Wilczek's original 2012 proposal (opens in a new tab) is often quoted without either bound, and that is the single most common way the idea arrives in a manufacturing roadmap in a form no physicist would recognise.
So what does this have to do with silicon wafer engineering? Two things, of very different sizes. The large one is that quantum devices have to be manufactured, and the most manufacturable qubit modality is a silicon quantum dot made on a 300 mm CMOS line — which turns an exotic physics question into a familiar process-control question. The small one is a metaphor: a fab is itself a driven, periodic system, and the discipline of holding a rhythm under perturbation is a real operational capability with real money attached. The ledger below keeps those two apart, along with everything else that gets said about this topic.
| The claim | Status | What the evidence actually says | The bound you must state | What it means for a fab now |
|---|---|---|---|---|
| Discrete time crystals exist | Established | Observed on a superconducting processor (Nature, 2022), in a trapped-ion chain (2016) and in a disordered dipolar spin system (2016); a continuous variant was observed in an atom-cavity system in 2022 | Driven systems only — equilibrium time crystals are ruled out by a published no-go theorem | Nothing directly. It is a phase of matter, not a component you can specify |
| Time crystals are a perpetual-motion or free-energy effect | False | No published result claims net energy extraction; the periodic drive supplies the energy throughout | The claim is about the period and robustness of the response, not about energy balance | Refuse it in any roadmap, capital proposal or vendor deck, on physics rather than on taste |
| Time-crystalline order will become quantum memory | Speculation, active research | Robustness of the subharmonic response has been demonstrated on small systems over finite times | System sizes and durations remain many orders from anything resembling a product specification | Do not budget capacity, headcount or a product line against it |
| Silicon can be manufactured to quantum-device tolerances on a 300 mm line | Established | Intel, imec and CEA-Leti have all published 300 mm spin-qubit fabrication using immersion and EUV lithography, standard modules and production-level process control | Yield, device-to-device uniformity and the cost of cryogenic screening remain the binding limits | This is the real, fundable link — and it runs on the process control you already operate |
| AI already runs periodic control loops in fabs | Established, and narrow | Virtual metrology, fault detection, run-to-run control and time-series anomaly detection are published and in production use | Each is bounded to a chamber, module or recipe family; none is a fab-wide controller | Extend the loops you have onto the time axis. Do not buy a fab brain |
| The fab will become self-sustaining and evolve without us | Speculation | No published evidence of a production line operating outside human change control | SEMI equipment and data standards, automotive quality management and customer qualification all require named human authority for process change | Treat as vision language. It is a different argument from this page's, and it is not a plan |
The ledger has a shape worth noticing. Everything in the "established" rows is either a physics result with no manufacturing implication, or a manufacturing result with no exotic physics in it. Nothing sits in the middle, and the middle is exactly where speculative roadmaps like to place themselves. The practical consequence for a fab is deflationary and useful: the correct response to a time-crystal headline is not a research programme, it is a check on whether your existing periodic control is as good as you think it is.
The phase-stability ladder, rung by rung
Five rungs measuring one thing: whether a periodic operating rhythm survives perturbation without amplifying it. Each rung carries its hallmarks, the signals a reviewer can check in an afternoon, the anti-pattern that traps fabs there, and what leaving costs.
The ladder below measures phase stability rather than organisational maturity: how well a line sees, holds and recovers its periodic rhythms. That is a deliberate choice, because it is the only property a fab shares with the physics in this page's title, and because it happens to be the property that coherence-grade manufacturing would eventually demand. Each rung is written for a process or controls engineer — the hallmarks are observable conditions, the diagnostic signals are checks you can run against your own telemetry this week, and the anti-pattern is the specific mistake most often made trying to leave that rung.
Select a rung
Every rung's full detail is in the page source — the selector only changes which panel is visible, so nothing here depends on JavaScript to exist.
Stage 1
Calendar cadence
33% of operators sit here
Calendar cadence is a fab whose periodic work — PM, wet clean, seasoning, qualification, calibration — fires on a fixed interval, with no measured account of what the process does between firings.
Rung 1 is not a fab without process control. It is a fab whose process control is blind to time. Statistical process control is running, monitor wafers are being measured, charts are being reviewed — and every one of those instruments treats a wafer processed two hours after a wet clean and a wafer processed two hundred wafers later as samples from the same population. They are not, and every process engineer in the building knows they are not. The knowledge simply lives in people rather than in data.
The cost of that blindness is paid in three currencies and it is rarely totalled. The first is monitor wafers and qualification time, spent generously because nobody can justify spending them precisely. The second is availability: PM intervals are set conservatively, because the alternative to a conservative interval is an excursion nobody can predict. The third and largest is argument. When yield moves, the conversation about whether it was the clean, the new focus ring, the material lot or the ambient is conducted in anecdote, and it is settled by seniority rather than by evidence.
This is a cheap rung to leave and an expensive rung to stay on. Leaving it requires no new tools, no new sensors and no new control loop — only a join. Take one module, take six months of metrology results, and plot them against the cycle position of the wafer that produced them. That single chart typically ends a running argument in the process area within a week, and it is the entire prerequisite for everything on rungs 2 to 5.
In practice
The Tuesday PM
A PECVD module in a 200 mm analogue fab runs a wet clean every 168 hours, always on a Tuesday, because that is when the maintenance crew has a window. Film thickness is measured on a monitor wafer immediately after the clean and again mid-week; both readings are in spec, so the chart is green. What the chart cannot show is that thickness climbs steadily across the week and the last two hundred production wafers before each clean run near the upper control limit. Downstream etch compensates without anyone deciding to, because the etch engineer has learned to expect it. Nothing is out of control, and nothing is under control either.
What it looks like
- PM and wet-clean intervals are set by calendar time or wafer count and rarely revisited
- Post-maintenance recovery is handled by a seasoning recipe and engineer judgement
- Monitor-wafer results are read as pass or fail, never as a trend within the cycle
- "Hours since PM" and "wafers since clean" are not fields any model or query can reach
Diagnostic signals you can check this week
- Ask for one chamber's film thickness plotted against wafers-since-clean for the last six months. If nobody can produce it within a day, you are on rung 1
- Check whether hours-since-PM exists as a queryable field in the MES or the EDA feed, or only as a row in the maintenance system
- Ask what the scrap and rework rate is on the first five wafers after a wet clean, by chamber. An unanswerable question is the finding
- Ask how the current PM interval was chosen and when it last changed. "It came with the tool" is a rung-1 answer
Anti-pattern · Buying a fab-wide platform to fix a chamber-level rhythm
The instinctive response to "we cannot see our cycles" is a data-lake programme with an eighteen-month horizon and a governance council. It reliably consumes a year without producing the one chart that would have changed the conversation in a week. The reason is that a platform built before anyone has used cycle state has to guess at what cycle state means — which events reset a cycle, which do not, how a partial clean differs from a full one. Those definitions are discovered by joining one module's data by hand and arguing about the result. Do that first; the platform's real shape is obvious afterwards and unguessable before.
What holds you here
Cycle position is invisible in data, so every discussion about drift is anecdote against anecdote and is settled by seniority.
Highest-leverage next move
Reconstruct the in-cycle trace for one chamber — metrology result against wafers-since-clean and hours-since-PM, six months deep — and agree what counts as a cycle reset.
Cost of leaving
- Effort
- 2–4 months
- Team
- One process engineer and one data engineer, both part-time
- Risk
- Low — the work is observational and nothing in production changes
- To next stage
- 2–4 months
If this is you, the next step is
A two-week engagement: one module, one cycle definition, one chart your process area will argue about.
Stage 2
Measured drift
30% of operators sit here
Measured drift is a fab that can see the shape of its own cycles — the sawtooth between cleans, the decay across pad life, the walk across source hours — but still corrects them by hand.
Rung 2 changes the conversation before it changes the process. Once the sawtooth is on a chart with a cycle axis, arguments that ran for years end in an afternoon — the film does climb across the clean cycle, the removal rate does decay with pad hours, the implant dose does walk with source life. Process engineers usually find that their intuitions were right in direction and wrong in magnitude, which is exactly the useful discovery, because magnitude is what a control loop needs.
What rung 2 does not yet have is authority. The correction still travels through a human: an engineer notices the drift, decides on an offset, files a change, waits for approval, and applies it at some point that has more to do with the meeting calendar than with the process. The lag between observing the drift and acting on it is typically measured in shifts or days, while the drift itself moves in wafers. This is the defining gap of the rung — the fab has become an excellent observer of a phenomenon it still cannot track in real time.
There is also a characteristic rung-2 temptation that deserves naming early. Having proven that drift correlates with cycle position, the obvious move looks like shortening the cycle: clean more often, PM more often, hold the process closer to centre. It works, and it is expensive. Availability falls, monitor-wafer consumption rises, and the fab has bought uniformity with capacity at an exchange rate nobody calculated. The alternative — teaching the control loop about the cycle instead of shrinking the cycle — costs engineering time rather than capacity, and it is what rung 3 is.
In practice
The pad-life chart that changed the argument
A CMP area had run a standing disagreement for two years: the polish engineers believed removal rate fell with pad hours, and the module owner believed the variation came from slurry lots. Both were partly right, and neither could prove it because removal rate was only ever plotted against date. Plotting the same data against pad hours, with slurry lot as a colour, resolved it in one chart — a clear decay curve with a step at each lot change. The immediate outcome was not a control change. It was that the conditioner recipe and the pad-change trigger stopped being negotiated in a meeting and started being argued from a curve.
What it looks like
- In-cycle traces exist per module and are reviewed as part of the normal process-engineering rhythm
- Cycle position — wafers since clean, hours since PM, pad hours, source hours — is a first-class queryable field
- Excursions get attributed to a specific cycle event more often than to unexplained noise
- Corrections are still manual: an engineer changes a recipe offset after a review meeting
Diagnostic signals you can check this week
- Ask a process engineer to show you the in-cycle trace for their module. If it appears in under a minute from a standing dataset, you are at least on rung 2
- Measure the elapsed time from a drift being visible on a chart to a recipe offset being applied. Days means the loop is human
- Ask whether the last three excursion reports named a cycle event as the cause, or defaulted to "tool variation"
- Check whether PM intervals have moved in the last year on the basis of measured indicators rather than a vendor recommendation
Anti-pattern · Tightening the calendar instead of the loop
The seductive fix at rung 2 is to shorten the cycle: clean earlier, PM earlier, qualify more often. Every one of those buys uniformity with availability and consumables, and none of them is ever reversed, because reversing a conservative interval requires the evidence the fab does not yet generate. Fabs accumulate these tightenings the way old code accumulates defensive checks — each one was locally reasonable and the aggregate is a capacity tax nobody owns. Before shortening an interval, ask whether the control loop could simply be told where in the cycle each wafer sits. That is a fortnight of engineering, not a permanent reduction in throughput.
What holds you here
The correction path still runs through a human on a meeting cadence, so the fab observes drift in wafers and responds to it in days.
Highest-leverage next move
Put cycle position into one virtual-metrology model and one run-to-run controller as an explicit feature, rather than leaving it as a hidden confound.
Cost of leaving
- Effort
- 3–6 months
- Team
- A process engineer, a data engineer and a named module owner
- Risk
- Low to medium — the work is analytical, but changing PM triggers touches qualification
- To next stage
- 3–6 months
If this is you, the next step is
We audit which cycle events are recorded, which are inferable and which are lost, module by module.
Stage 3
Phase-locked control
23% of operators sit here
Phase-locked control is where periodic structure lives inside the control loop: prediction and run-to-run correction both know where in the cycle a wafer sits, and cadence is triggered by predicted state rather than by the calendar.
Rung 3 is the first rung where the fab holds phase rather than merely watching it. The mechanics are unglamorous and well documented. Virtual metrology gets cycle position as a feature, which typically removes a large, systematic component from its error and — more usefully — makes its uncertainty honest, because the model can now express that it knows less about a wafer three hours after a clean than about one mid-cycle. Published work on virtual metrology in mass production and on uncertainty-aware estimation from small samples both point the same way: the value is less in the point prediction than in a calibrated confidence a controller can act on.
The run-to-run controller is the second half. A standard exponentially weighted moving average filter is designed to track a slow drift, and a wet clean is not a slow drift — it is a step. Feeding a step into a filter tuned for drift produces exactly the pathology the control literature describes: a correction that overshoots, then a correction of the correction, then a lot or two of ringing before the loop settles. The fix is not more aggressive tuning; the stability analysis of EWMA run-to-run control makes clear that raising the gain to chase a disturbance moves the loop toward oscillation rather than toward centre. The fix is to tell the controller that a reset happened, and to give it a prior for what usually follows.
The organisational shift at rung 3 is that cadence stops being a maintenance decision and becomes a control decision. When the trigger for a clean is a predicted state rather than a date, the maintenance schedule, the dispatch policy and the process model are all reading the same variable. That is a genuine coordination change and it needs a genuine owner, because the first time a condition-based trigger asks for a clean on a Friday afternoon during a hot-lot push, somebody has to decide — and that decision should be a written policy, not a corridor conversation.
In practice
The first-wafer effect that stopped costing wafers
An etch module ran two send-ahead wafers after every chamber clean, scrapping both, because the first production lot had historically come back with CD outside the tightened post-clean limits. Adding wafers-since-clean to the virtual-metrology model and a learned post-clean prior to the CD run-to-run controller let the loop start from roughly the right offset instead of discovering it. The send-aheads did not disappear — qualification still required one — but the second was retired, and the CD spread on the first production lot after a clean narrowed enough that the tightened post-clean limits were eventually merged back into the standard limits. The saving was counted in send-ahead wafers and in qualification minutes, both of which the module owner already reported.
What it looks like
- Cycle position is an explicit input to the virtual-metrology model, not a hidden confound in its residuals
- The run-to-run controller carries a post-event prior, so the first lot after a clean is not treated as a step change
- Clean and PM triggers are condition-based, with a calendar backstop that is itself reviewed
- Monitor-wafer sampling is adaptive — dense immediately after a perturbation, sparse mid-cycle
Diagnostic signals you can check this week
- Ask whether cycle position appears in the feature list of any deployed virtual-metrology model, and check the residuals for a sawtooth if it does not
- Look at the run-to-run correction magnitudes for the first three lots after a clean. A large correction followed by a reversal is ringing, not tracking
- Ask what would happen if a condition-based clean trigger fired during a hot-lot push, and whether the answer is written down
- Check whether monitor-wafer sampling density varies with cycle position or is uniform by policy
Anti-pattern · Raising the controller gain to chase the sawtooth
When a run-to-run loop lags a periodic disturbance, the fastest-looking fix is more gain — respond harder to each deviation. The stability analysis of EWMA run-to-run controllers in semiconductor processes is explicit that this trades tracking speed for stability margin, and a loop that oscillates produces a worse distribution than one that lags. The correct move is informational rather than aggressive: give the controller the cycle event, give it a prior for the post-event offset, and leave the gain where the stability analysis says it belongs. Fabs that learn this the hard way usually learn it from a fortnight of alternating over- and under-etched lots that nobody could attribute.
What holds you here
The loop holds phase within a module but has no account of what happens when the disturbance is larger than the loop — an unplanned down, a part swap, a material-lot change.
Highest-leverage next move
Start measuring re-lock time: the wafers or hours between a perturbation and the process returning inside its normal band, per module and per perturbation type.
Cost of leaving
- Effort
- 6–12 months
- Team
- Process engineer, controls engineer, ML engineer, plus qualification support
- Risk
- Medium — the first controller change needs a drilled revert and a qualification path
- To next stage
- 9–18 months
If this is you, the next step is
One module, one controller, one qualification pack — typically a single quarter.
Stage 4
Perturbation-resilient operations
11% of operators sit here
Perturbation-resilient operations is where the fab measures how long its rhythm takes to return after a shock, manages that recovery time as a number, and knows whether a disturbance amplifies downstream or dies out.
Rung 4 is where the unit of management changes from the deviation to the recovery. A rung-3 fab can tell you its process capability; a rung-4 fab can tell you that a focus-ring change on a given etch module costs, on average, a specific number of wafers before critical dimension is back inside its normal band, that the number has fallen over the last two quarters, and what the intervention was that moved it. That is a different kind of claim, and it is the one that matters for anything time-critical, because a fab's real variability is dominated by its perturbations rather than by its steady state.
The second rung-4 capability is propagation. A disturbance at deposition does not stay at deposition; it arrives at etch as an incoming variation, and whether the etch loop attenuates it or amplifies it is a property of how the two loops are tuned relative to each other. Most fabs discover coupled-loop amplification the same way — as a yield signature that no single module owns, three weeks after the fact. Making propagation a monitored quantity turns that from a forensic exercise into an alarm, and it is the point at which cross-module control stops being a slogan.
This is also the rung where certification stops being background noise and becomes design input. Semiconductor manufacturing runs inside a dense frame of equipment, data and quality standards — the SEMI standards estate for equipment reliability and data acquisition, automotive quality management for parts that go into vehicles, and customer-specific qualification for anything that ships to a named account. Every one of those frames asks the same underlying question of an automated recovery: who authorised it, on what evidence, and can you reconstruct the decision later. A rung-4 fab answers by producing the evidence as a by-product of the recovery procedure. A fab that automates recovery first and documents it afterwards discovers during an audit that it has automated something it cannot defend.
In practice
The fourteen-hour requalification that became four
A deposition module's post-PM qualification ran as a fixed sequence: a set number of seasoning wafers, then a fixed monitor plan, then a review, typically fourteen hours end to end regardless of what the PM had involved. Timing the sequence for the first time revealed that most of it was waiting — for a metrology slot, for an engineer to review a chart, for a shift handover. Redesigning the qualification around measured re-lock rather than a fixed wafer count, with the metrology slot reserved in advance and the review criteria written as thresholds instead of judgement, took the median to roughly four hours. No process capability changed. What changed was that recovery was treated as a designed procedure with a clock on it.
What it looks like
- Re-lock time after PM, part swap and material-lot change is measured and trended per module
- Excursion propagation is tracked: whether one module's disturbance grows or attenuates at the next step
- Requalification is a designed, timed procedure with an evidence pack, not an improvised sequence
- A change to a controller prior goes through the same change control as a change to a recipe
Diagnostic signals you can check this week
- Ask for the median and worst-case re-lock time on your three most constrained modules, by perturbation type. Rung 4 has the number; rung 3 has a story
- Check whether any excursion review in the last year quantified propagation to the next step rather than describing it
- Ask whether a controller prior can be changed without a change record. If it can, the loop is outside change control
- Time one requalification end to end and count how much of it is waiting rather than processing
Anti-pattern · Automating recovery before defining authority
Once re-lock is measured, automating it looks obvious — let the system season, qualify and resume without waiting for a person. The failure is not technical. It is that recovery decisions carry qualification consequences, and qualification consequences carry customer and certification consequences, so the question "who authorised resuming production" has to have an answer with a name on it. Fabs that automate the sequence and leave the authority implicit end up in one of two places: a suspended automation after the first disputed lot, or an audit finding. Write the authority policy — what the system may resume unattended, in what band, with what evidence, and what it must escalate — and then automate inside it.
What holds you here
Recovery is fast and evidenced, but the fab has no reason to hold tolerances tighter than its current products demand, so the discipline plateaus at the product's requirement.
Highest-leverage next move
Decide deliberately whether any product line justifies coherence-grade tolerances — and if none does, keep rungs 1–4 paying rather than manufacturing a reason to go further.
Cost of leaving
- Effort
- 12–24 months
- Team
- Controls and process integration, a quality and qualification lead, an operations owner
- Risk
- Medium to high — the constraint moves from engineering to qualification and change control
- To next stage
- 24+ months, and often correctly never
If this is you, the next step is
A two-week measurement on three modules, using telemetry you already record.
Stage 5
Coherence-grade manufacturing
3% of operators sit here
Coherence-grade manufacturing is a line held tightly enough, and evidenced well enough, to make devices whose function depends on quantum coherence — the standard the published 300 mm silicon spin-qubit programmes are built to.
Rung 5 is narrow, and its narrowness is the point. Roughly three per cent of lines are anywhere near it, and for most fabs that is the correct answer rather than a gap to close. What makes the rung worth describing is that its requirements are not exotic in kind — they are the rung-1-to-4 disciplines carried further than a logic or memory product would ever justify. The published 300 mm silicon spin-qubit work is unambiguous on this: the devices were made with immersion and extreme-ultraviolet lithography, standard high-volume process modules and production-level process control, on lines that were built for transistors.
The specific tolerances are instructive because they are numbers rather than adjectives. A 300 mm silicon MOS qubit platform reported uniform critical dimensions down to 30 nm with a standard deviation of about 1.6 nm. An isotopically purified silicon-28 epitaxial layer was grown on 300 mm substrates at better than 99.992 per cent purity, to the same quality requirements as the natural-abundance epilayers used in the same pre-industrial CMOS facility. A foundry-fabricated two-qubit unit cell has been reported above 99 per cent fidelity in all operations. None of these is a physics breakthrough in the manufacturing sense; each is process control held to a tolerance a conventional product does not need.
The honest caution at rung 5 is about demand, not physics. The market that would consume coherence-grade capacity is small, research-led and moving on its own schedule, and a fab that builds capacity against it is taking a market bet dressed as a technology bet. The defensible posture is optionality: keep rungs 1 to 4 paying on the products you actually ship, hold a research partnership or a shuttle arrangement so the capability is reachable, and require any proposal to state its demand bound as explicitly as its technical one.
In practice
The wafer prober that changed the yield conversation
Silicon spin-qubit devices were historically characterised a few at a time in a dilution refrigerator, which meant yield and process-variation statistics were built from tiny samples and arrived months after the wafers were made. Intel's published work describes testing single-electron devices across full 300 mm spin-qubit wafers using cryogenic wafer-scale probing, explicitly to keep the scale of testing in step with the scale of fabrication and to improve statistics like qubit yield and voltage variation. The lesson generalises well beyond quantum devices: when the measurement cadence is slower than the process cadence, you are not controlling the process, you are auditing it after the fact.
What it looks like
- Isotopic and material purity are controlled and measured as process parameters, not assumed from a certificate
- Function-level screening happens at wafer scale rather than on a handful of dies at end of line
- Defect, interface-state and charge-noise budgets are stated numerically and have named owners
- The periodic control discipline of rungs 1–4 is treated as a precondition, not as a parallel programme
Diagnostic signals you can check this week
- Ask whether any material purity specification is measured in-house or accepted on a supplier certificate
- Ask what fraction of a wafer's electrically active structures are measured before end of line
- Check whether charge-noise, interface-state or defect budgets exist as numbers with owners, or only as qualitative goals
- Ask whether a coherence-grade proposal in the building states a demand bound as clearly as a technical one
Anti-pattern · Booking a quantum line item without a qualification plan
The recognisable failure at this rung is a capital proposal for coherence-grade capability whose technical section is detailed and whose qualification and demand sections are a paragraph each. It passes because the technology is genuinely real and the reviewers are not physicists. It fails eighteen months later, when the line exists, the qualification path was never designed, and the customer who would have consumed the capacity is still running research volumes. Require every visionary proposal to carry three bounds in the same font as the vision: what the physics permits, what certification and qualification will require, and who has committed to buy the output.
What holds you here
Demand rather than physics: the device market that would consume coherence-grade capacity is small and research-led, so capacity built against it may idle.
Highest-leverage next move
Buy optionality through research partnership and shuttle runs rather than through dedicated capacity, and keep the rung-1-to-4 disciplines earning on current products.
Cost of leaving
- Effort
- Multi-year, and correctly optional
- Team
- Process integration, materials, cryogenic or function-level test, plus a research partner
- Risk
- Concentrated — the technical risk is manageable and the demand risk is not
If this is you, the next step is
We stress the physics, qualification and demand bounds separately, and say which one is load-bearing.
Two features of this ladder differ from a conventional adoption curve and are worth stating explicitly. First, rung 5 is not the goal. For the overwhelming majority of lines, stopping deliberately at rung 4 is the correct commercial answer, and a page that implied otherwise would be selling a market bet as an engineering one. Second, the ladder is not monotonic in the usual way: a fab can hold rung 3 on its deposition modules and rung 1 on its facilities systems, and the fab-level rung is the one that governs the interactions, not the best module.
Where silicon lines actually sit on this ladder
The distribution across the five rungs, why the rung 2 → 3 step is the expensive one, and why the top rung is genuinely rare rather than merely aspirational.
Most silicon lines sit on rungs 1 and 2 — able to run excellent statistical process control while remaining structurally blind to where in a cycle a given wafer was processed. The distribution below is illustrative rather than surveyed: it synthesises what the published process-control literature, the trade press and the quantum-device fabrication papers collectively imply about how far cycle-aware control has actually spread. Treat it as a shape, not a census.
Illustrative distribution of silicon lines across the phase-stability ladder
Rungs 1 and 2 hold roughly two-thirds of lines between them. The step from rung 2 to rung 3 is the expensive one because it is the first that changes a control loop rather than a chart, and therefore the first that touches qualification.
Share of lines
- 33% — 1 · Calendar cadence
- 30% — 2 · Measured drift (sees the cycle, corrects by hand)
- 23% — 3 · Phase-locked control
- 11% — 4 · Perturbation-resilient
- 3% — 5 · Coherence-grade
1.6 nm
Critical-dimension standard deviation reported on a 300 mm silicon MOS qubit platform at IEDM 2020
imec
> 99%
Single- and two-qubit control fidelities on a 300 mm foundry-fabricated unit cell, verified by gate set tomography
Diraq and imec
12
Quantum dots in each linear array on Intel's Tunnel Falls test chip, fabricated with EUV on a 300 mm line
Intel
The reason rung 2 is a plateau rather than a waypoint is structural. Getting to rung 2 requires a join and a chart; getting to rung 3 requires changing a control loop, and in a fab a control-loop change is a qualification event. That is the whole difference. The engineering to add cycle position to a virtual-metrology model is measured in weeks — the published work on virtual metrology in mass-produced processes (opens in a new tab) and on uncertainty-aware estimation from small samples (opens in a new tab) has done most of the method development already. The qualification path, the revert drill and the change record are what take a quarter, and they are also what make the change survivable.
The three per cent at rung 5 is a real number rather than a rhetorical one, and it is not distributed the way people assume. The lines that have demonstrated coherence-grade fabrication are not exclusively leading-edge logic fabs; they include research-institute 300 mm pilot lines such as imec's (opens in a new tab) and national-laboratory facilities such as CEA-Leti's, alongside Intel's production infrastructure. What they share is not node size but tolerance discipline, and tolerance discipline is buildable at any node.
How a fab's periodic rhythm breaks, and how it comes back
The mechanism the ladder climbs: the scheduled drive, the perturbations that break phase, and the loop that returns the process to centre — with the places phase is lost marked.
A fab loses phase in one of four ways, and gets it back through one loop. The four ways are an unplanned tool-down, a hardware change such as a focus-ring or pad swap, a consumable or material lot change, and a dispatch decision that breaks the processing sequence. The single recovery loop runs from cycle-state telemetry through prediction, attribution and human authority to a logged resumption of cadence. Almost every phase-stability improvement a fab can make is a change to one node of that diagram, and knowing which node is most of the value of drawing it.
The re-lock loop
Three lanes: the scheduled rhythm the fab is trying to hold, the perturbations that break it, and the loop that returns the process to centre. The rung you are on is decided by how much of the bottom lane exists — most fabs have the top lane, half have started measuring the middle one, and few time the bottom one.
- Data & feeds
- System-of-record action
- AI / model
- Where value leaks
- Human in the loop
The process, in words
- The drive is the rhythm the fab schedules for itself: a preventive-maintenance and wet-clean calendar, a seasoning recipe that conditions the chamber afterwards, a qualification and monitor-wafer plan that gauges it back to centre, and a run-to-run controller that trims each lot. Every fab has this lane, and at rung 1 it is the only lane that exists in data.
- The perturbation lane is what actually breaks phase: an unplanned tool-down that voids the calendar, a hardware change such as a focus ring or a CMP pad that resets the process to an unknown starting point, a consumable or material lot change that shifts the gauge underneath the control chart, and a dispatch decision — a hot lot, a rework loop — that breaks the processing sequence the controller assumed. Rung 2 is where these become measured events rather than remembered ones.
- The re-lock loop is the recovery path. Cycle-state telemetry says where in the cycle the chamber is; a cycle-aware prediction says what the process should be doing there; attribution decides whether the deviation is drift, a step change or a genuine excursion; a named engineer holds the authority to accept, override or requalify; and the resumption is logged as evidence. Rung 3 builds the first three nodes, rung 4 times the whole path and governs the authority, and rung 5 requires the same loop at tolerances a conventional product would never justify.
Step-by-step insights
- The calendar is a bet, and it is usually a losing one in both directions
- A fixed PM interval bets that the process ages at a constant rate. It does not: chamber condition depends on what ran, how much, at what power and with what materials. The bet loses twice. Cleaning too early spends availability and consumables on a chamber that was still in control, and every conservative interval a fab adopts after an excursion is permanent because reversing it requires evidence the fab does not generate. Cleaning too late produces the excursion that causes the next tightening. The escape is not a better calendar; it is a trigger that reads condition, with the calendar retained as a backstop so a sensor failure cannot defer maintenance indefinitely.
- Seasoning is a control action that nobody controls
- The seasoning or conditioning recipe after a clean is one of the least examined items in a fab. It was usually set once, at tool install, by a vendor engineer, and it has run unchanged since — a fixed number of wafers with a fixed recipe, applied identically after a five-minute in-situ clean and a full wet clean with a kit change. Two perturbations of very different magnitude get the same recovery, which guarantees that one is over-treated and the other under-treated. Instrumenting the post-seasoning trajectory is often the highest-yield single measurement on this whole diagram, because it converts a fixed cost into a variable one and immediately shows which cleans genuinely need the full sequence.
- The gauge moves too, and a material lot change is the usual reason
- The most confusing excursions in a fab are the ones where the process did not change and the measurement did. A new slurry lot, a new precursor batch, a recalibrated metrology tool or a replaced correlation standard can all shift what the control chart reads without shifting what the chamber does. This is the specific failure that makes a run-to-run controller dangerous: the loop faithfully corrects the process to match a moved gauge, and it does so quietly, so the deviation only surfaces when the next perturbation exposes it. Lot identity has to be a first-class variable in the process model for exactly this reason, and it is why rung 5 controls material purity in-house rather than accepting it on a certificate.
- Attribution is the node that decides whether AI helps or hurts
- The three cases — slow drift, a step change and a genuine excursion — call for three different responses, and confusing them is how control loops make things worse. Drift wants a gentle correction; a step change wants a re-basing with a prior; an excursion wants the loop held and a human called. This is where published methods earn their place: fault detection and classification on tool sensor traces, anomaly detection on multivariate process time series, and unsupervised wafer-scale variability analysis all exist to make this distinction earlier and more reliably than a control chart can. Note what the AI is doing here. It is not deciding; it is classifying the disturbance so that the right pre-agreed response fires.
- Authority is a policy artefact, and it is what an auditor will read
- The engineer-authority node is the one that visionary architectures like to remove, and it is the one that certification will not let you remove casually. A change to what a process does, or to when a chamber is qualified to run production, has to be attributable to a named authority under a written policy, with a reconstructable record — that is the common demand behind SEMI's equipment and data standards, automotive quality management systems and customer-specific qualification alike. The rung-4 move is not to delete this node but to define it precisely: what the loop may resume unattended, inside what band, on what evidence, and what it must escalate. Automating inside a written policy is defensible. Automating in the absence of one is an audit finding waiting for a date.
- Re-lock time is the number the whole diagram exists to produce
- If you take one metric from this page, take this one: the elapsed wafers or hours between a perturbation and the process returning inside its normal band, measured per module and per perturbation type. It is readable from telemetry you already record, it is comparable across modules in a way that capability indices are not, and it responds to exactly the interventions this diagram describes. It is also the metric that makes the coherence-grade conversation concrete, because a line that cannot state its re-lock time is not in a position to promise anyone the stability a quantum device would need.
Reading the diagram against the rungs gives a blunt diagnostic. If only the top lane exists in your data, you are on rung 1. If the middle lane is recorded and attributed, you are on rung 2. If the first three nodes of the bottom lane are automated, you are on rung 3. If the whole bottom path is timed and the authority node is written down, you are on rung 4. Rung 5 adds no new nodes at all — it only tightens the tolerances every node is held to, which is the most reassuring finding on this page.
Where periodic order actually lives in a fab
Module by module: the rhythm each process area runs on, what perturbs it, the signal that exposes phase, the loop that owns it, and the rung at which it can be closed.
Periodic order in a fab is not one rhythm but roughly seven, each with its own period, its own perturbations and its own owner. Deposition runs on a clean cycle measured in wafers; CMP runs on a pad-life curve measured in polish hours; lithography runs on a calibration and reticle cadence measured in exposures; facilities run on maintenance windows and, more awkwardly, on the seasons. Confusing them is the reason fab-wide "drift" initiatives produce so little: the interventions are module-specific even though the vocabulary is shared.
| Process area | The periodic structure | What perturbs it | Signal that exposes phase | Control loop that owns it | Closes at |
|---|---|---|---|---|---|
| Deposition (CVD, PECVD, ALD) | Wafers-since-clean sawtooth between in-situ and wet cleans | Wet clean, kit change, precursor lot, chamber seasoning length | Thickness and uniformity against wafers-since-clean; RF and impedance traces | Thickness R2R with a post-clean prior, cycle-aware virtual metrology | Rung 3 |
| Etch | Chamber conditioning cycle and PM interval | Wet clean, focus-ring or liner replacement, chamber-to-chamber swap | CD and depth drift against cycle position; optical emission endpoint shift | CD run-to-run control plus fault detection on the sensor traces | Rung 3 |
| Lithography | Scanner calibration and qualification cadence; reticle exchange cycle | Baseline recalibration, lens heating, reticle swap, resist lot | Overlay and focus residuals across an exposure sequence | Overlay run-to-run control and the scanner's own recalibration schedule | Rung 4 |
| CMP | Pad-life decay curve and conditioner-disc cycle | Pad change, slurry lot, conditioner wear, break-in wafers | Removal rate against pad hours, with slurry lot as a covariate | Removal-rate R2R plus an explicit pad-life model | Rung 3 |
| Implant and thermal | Source life and beam-tune cadence; furnace tube campaigns | Source or filament change, tube clean, boat replacement | Dose uniformity against source hours; sheet resistance against campaign position | Dose R2R with SPC on the campaign, condition-based tube scheduling | Rung 3 |
| Metrology and test | Sampling-plan cadence and gauge requalification interval | Gauge drift, standard replacement, recipe recalibration | Gauge repeatability over time; correlation-wafer trend against requal date | Metrology SPC feeding the virtual-metrology confidence budget | Rung 2 |
| Facilities and sub-fab | Chiller, abatement and ultrapure-water maintenance cycles; seasonal ambient | Maintenance windows, weather, grid events, house-vacuum load changes | Temperature, humidity and pressure periodicity correlated against excursions | Facility control with fab-level correlation into process excursions | Rung 4 |
Two entries in that table are the ones fabs most often skip, and both are skipped for the same reason — they are owned by someone other than process engineering. Metrology and test sits at rung 2 in the right-hand column because it is genuinely easy to close, and yet gauge requalification cadence is routinely the last thing instrumented, with the result that months of "process drift" turn out on inspection to have been gauge drift. Facilities sits at rung 4 because the correlation is fab-wide and seasonal, which means nobody sees it from inside a single module, and it takes a full year of data before the pattern is even visible.
One boundary is worth naming here, because a reader arriving from a neighbouring question will otherwise look for it on this page. This map is about the time axis: how one module behaves across its own cycle. The orthogonal problem — how nominally identical tools diverge from each other at the same moment — is a different ledger with different signals and different remedies, and it is covered in the autonomous wafer fleets page. Attacking chamber matching with cycle-aware control, or cycle drift with fleet matching, is the most common way a well-resourced programme spends a year in the wrong dimension.
The four dimensions that set your rung
Phase stability is not one number. Four dimensions gate each other, and the lowest is the real rung — on this ladder, almost always the first one.
Phase stability is scored on four dimensions — cadence instrumentation, phase control, perturbation recovery and coherence-grade discipline — and the lowest of the four is the real rung, because each gates the one after it. A sophisticated controller reading a feed that cannot express cycle position is not a rung-3 capability with a data problem; it is a rung-1 capability with an expensive controller, and it will behave worse than the manual process it replaced, because it corrects confidently in the wrong direction.
Cadence instrumentation
Whether cycle position exists as a first-class, queryable variable — hours since PM, wafers since clean, pad hours, source hours, campaign position — and whether the events that reset it are agreed. This is the cheapest dimension to fix and the most common binding constraint. It is also the one that gets scored optimistically, because the data usually exists somewhere; the question is whether a model can reach it without a human assembling a join.
Phase control
Whether the control loop acts on cycle position or is merely exposed to it. The two tells are the run-to-run controller's behaviour on the first lot after a reset, and whether maintenance triggers read condition or a date. Note the failure direction here: the risk is not an under-powered loop, it is an over-confident one. The stability analysis of EWMA run-to-run control (opens in a new tab) is the standard reference for why chasing a periodic disturbance with gain produces oscillation rather than tracking.
Perturbation recovery
Whether re-lock time is measured, trended and owned, and whether disturbance propagation across coupled loops is visible before it becomes a yield question. This dimension is where a fab's real variability lives — steady-state capability is a comfortable number, and perturbation behaviour is the one that determines whether a tight tolerance is actually holdable in production rather than in a capability study.
Coherence-grade discipline
Whether materials, interfaces and function-level behaviour are controlled as process parameters rather than accepted as inputs. This is the only dimension that is genuinely optional. It is scored here because it is what separates a line that could host quantum-device work from one that could not, and because the first two steps in it — controlling lot identity and densifying in-line electrical measurement — pay for themselves on conventional products long before any coherence-grade product exists.
Diagnosing the real constraint
Plot cadence instrumentation against control authority. The quadrant names the next investment — and note that the two failure quadrants fail in opposite directions, so the same intervention would make one of them worse.
Blind autopilot
- A loop acting confidently on signals that cannot see the cycle
- Corrects the sawtooth as if it were noise, and rings
- Fix: reduce authority first, instrument second — in that order
Phase-locked
- Cycle-aware prediction with a controller that acts on it
- The constraint moves to recovery and propagation
- Fix: start timing re-lock, per module and perturbation type
Calendar fab
- Neither the signal nor the loop exists yet
- Common, and cheap to leave
- Fix: one module, one cycle definition, one chart
Watched, not held
- The drift is visible and the response is a meeting
- The most common position and the highest-leverage one
- Fix: put cycle state into one existing control loop
The two failure quadrants are worth separating carefully, because a generic "more AI" recommendation makes one of them considerably worse. In the watched-but-not-held quadrant the signal is good and the loop is slow, so adding control authority is exactly right. In the blind-autopilot quadrant the loop is already acting on a signal that cannot represent what is happening, and adding authority accelerates the damage. The order of operations is not a stylistic preference: instrument, then verify the instrument represents the cycle, then close the loop.